1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including a semiconductor memory, for example, a DRAM, and having a self-test function of the semiconductor memory, and a semiconductor integrated circuit device such as system LSI having a microcomputer or a logic circuit, and a semiconductor memory in a mixed relationship with each other, and having a self-test function of the semiconductor memory, and the manufacturing method thereof. More particularly, it relates to a memory self-test technique and a burn-in test technique in these semiconductor integrated circuit devices.
2. Prior Art
With recent improvements (implementation of higher density and higher integration) in a semiconductor integrated circuit device, a so-called system LSI in which a plurality of functional blocks are integrated into one chip has become markedly prevalent. Especially, attention has been given to a mixed LSI in which a large-scale logic circuit and a large-scale DRAM are integrated into one chip in recent years. With this trend, there has earnestly been conducted a study of a function circuit for carrying out the self-test of each functional block within the chip (BIST circuit: Built In Self Test circuit).
FIG. 13 shows one example of the configuration of a conventional BIST circuit. This is an example of a BIST circuit for self-testing a large-capacity memory mounted within a chip. Referring to FIG. 13, a data generator 1 generates a test data 3 required for the test of a memory 2, and an expected value data 4 in the test, and supplies the test data 3 to the memory 2, while supplying the expected value data 4 to a data comparison circuit 5.
An address generator 6 generates an address signal 7 required for the test of the memory 2, and supplies it to the memory 2. Also, the address generator 6 supplies address phase information 8 of the address signal 7 to a phase control circuit 9.
The above-described address phase information is a signal which presents, for example, "H (high level)" when the value of the address becomes "0". The address is generated arbitrarily, which necessitates a signal for indicating at which timing the address switches. The signal for indicating the switching of the address is the address phase information 8. It is the phase control circuit 9 which generates memory control signals 11 such as write enable (WE) signal, output enable (OE) signal, row address strobe (RAS) signal, and column address strobe (CAS) signal required for writing to and reading from the memory 2 on the basis of this signal.
The phase control circuit 9 sends data phase information 10 back to the data generator 1 so that the test data 3 and the expected value data 4 are outputted from the data generator 1 at a required timing in accordance with the address signal 7. The phase control circuit 9 also generates the memory control signals 11 such as WE signal, OE signal, RAS signal, and CAS signal required for the test of the writing to and reading from the memory 2, and supplies them to the memory 2.
The data phase information 10 is a signal as described below. That is, a signal required for writing to and reading from the memory 2 is generated on the basis of the signal of the address phase information 8 (ex., a signal which presents "H" when the value of the address becomes "0") at the phase control circuit 9. In this step, the data to be written to the memory 2 and the data to be read from the memory 2 are both required to be generated in accordance with the timing. It is the data phase information 10 which indicates the timing. Data is generated from the data generator 1 on the basis of this signal.
The data generator 1, the address generator 6, and the phase control circuit 9 are capable of generating data of plural kinds of patterns, and are controlled by a mode control circuit 12.
The test of the memory 2 is carried out in the following procedure. That is, the test data 3 is written to the address indicated by the address signal 7 of the memory 2. Thereafter, data is read from the same address of the memory 2. Then, the comparison between the read data, i.e., memory actual output data 13 and the expected value data 4 is performed by the data comparison circuit 5. When the expected value data 4 matches the memory actual output data 13, a pass/fail flag signal 5A outputted from the data comparison circuit 5 has a value indicating the pass state (ex., "L (Low level)", while in the case of mismatch therebetween, the pass/fail flag signal 5A has a value indicating the fail state (ex., "H"). It is noted that, as the test results, the pass/fail flag signal 5A is outputted, and a failed address is also outputted at the time of fail. The failed address denotes the output of the address generator 6 when a fail has occurred, i.e., address data. The procedure varies differently depending on the configuration of a BIST circuit. For example, in the case where the pass/fail flag signal 5A is set to present "H" at the time of fail, and the next address is to be accessed after evaluation, the output obtained by performing an AND operation between the output of the address generator 6 and the pass/fail flag signal 5A can be properly provided.
FIG. 14 shows a block diagram of a logic circuit/DRAM mixed system LSI as semiconductor integrated circuit device. Referring to FIG. 14, a system LSI 100 is comprised of a logic circuit 101, a DRAM 102, selectors 103 , 104, 105, 106, 107, and 108 switched by a mode switching signal 14 outputted from the logic circuit 101, input terminals 109, 110, 111, and 112, a clock terminal 113, and output terminals 114 and 115. It is noted that a microcomputer may sometimes be used in place of the logic circuit.
In the system LSI 100 having the above-described configuration, the signals inputted from the input terminals 109 to 112 are supplied to the logic circuit 101, while they are each supplied to its corresponding one of respective input ends of the selectors 103 to 106. Also, a part of the output of the logic circuit 101 is supplied to the other input end of each of the selectors 103 to 106. Of the respective two inputs of the selectors 103 to 106, the ones selected by the mode switching signal 14 are supplied to the DRAM 102 as input. Also, the output of the DRAM 102 is supplied to the one of two input ends of each of the selectors 107 and 108, while the remainder of the output of the logic circuit 101 is supplied to the other of two input ends of each of the selectors 107 and 108. Of the respective two inputs of the selectors 107 and 108, the ones selected by the mode switching signal 14 are supplied to the output terminals 114 and 115, respectively. Further, a clock is supplied in common from the clock terminal 113 to the logic circuit 101 and the DRAM 102. However, it can be properly supplied thereto separately.
In this case, input signals to the DRAM 102 are selected depending on the time of normal operation and the time of test by the mode switching signal 14. Further, as for the output terminal, switching is performed between output from the logic circuit 101 and output from the DRAM 102. Specifically, during the test of the DRAM 102, switching is performed so that the input signals from the input terminals 109 to 112 are given to the DRAM 102, and the output signals of the DRAM 102 are outputted from the output terminals 114 and 115, respectively. On the other hand, at the time of normal operation, the selectors 103 to 106 switch so that signals are inputted from the logic circuit 101 to the DRAM 102, while the selectors 107 and 108 switch so that the signal of the logic circuit 101 is outputted.
However, the circuit configuration cited in Prior Art has the following four problems.
A first problem is as follows: that is, the direct comparison between the expected value data 4 and the memory actual output data 13 is performed in the data comparison circuit 5 to output the pass/fail flag signal 5A. Accordingly, the circuit size increases by multiples of the number of bits with an increase in data bus width (number of bits) of the memory 2.
A second problem is as follows: that is, an increase in data bus width (number of bits) of the memory 2 increases the circuit size of the data comparison circuit 5. Accordingly, there are many gate circuits to be passed between the instant when data is inputted to the data comparison circuit 5 and the instant when the pass/fail flag signal 5A is outputted. Consequently, a long period of time is required for the step between the instant when the memory actual output data 13 is outputted from the memory 2 and the instant when the pass/fail flag signal 5A is produced. This results in a difficulty in testing the memory operating with a high-speed clock at a high speed.
A third problem is as follows: that is, such configuration is adopted so that the pass/fail flag signal 5A outputted from the data comparison circuit 5 is produced as it is from the output terminal as the test result. Accordingly, for example, in the case where the data comparison circuit 5 fails, and only either one of the data "L" indicative of pass, or the data "H" indicative of fail is outputted as pass/fail flag signal 5A, not only the memory test using a circuit for self-test cannot be performed at all, but also a good product may be mistaken for a defective product under certain circumstances.
A fourth problem is as follows: that is, the system LSI as a microcomputer or logic circuit/DRAM mixed semiconductor integrated circuit device has no access-only terminal of the DRAM. Accordingly, in the test of such a system LSI, as shown in FIG. 14, the input signal to the DRAM 102 is required to be switched depending on the time of normal operation and the time of test by the mode switching signal 14. Further, the switching between the output from the logic circuit 101 and the output from the DRAM 102 is required to be achieved as for the output terminals 114 and 115. It is noted that the clock is sharable.
In such a system LSI, when a burn-in test, i.e., a high-temperature bias test is carried out, it is very difficult to share the input pattern between the logic circuit 101 and the DRAM 102. Further, checking of each output data of the logic circuit 101 and the DRAM 102 cannot be performed simultaneously. This is attributable to the following fact; that is, the input pattern for effecting the operation of the DRAM 102 has been previously determined except for the data to be written into the DRAM 102. Accordingly, it is close to impossible to effect the operation of the entire logic circuit 101 with the pattern.
This causes the burn-in tests of the logic circuit 101 and the DRAM 102 to be carried out separately in two steps.
FIG. 15 shows a flowchart of the manufacturing steps of a semiconductor integrated circuit device in the case where the burn-in tests of the logic circuit 101 and the DRAM 102 are carried out separately. Referring to FIG. 15, a step 121 represents a diffusion step for performing a diffusion process and the like; a step 122 represents a probe test step; a step 123 represents an assembly step for performing bonding and the like; a step 124 represents a logic burn-in test step for performing a burn-in test of the logic circuit 101; a step 125 represents a memory burn-in test step for performing a burn-in test of the DRAM 102; a step 126 represents a final test step; a step 127 represents a shipment test step; and a step 128 represents a shipment step.
It is noted that the probe test denotes a test on a wafer, while the final test denotes a test in the state where a LSI chip has been assembled into a package. The final test often becomes an actual shipment test. Also, shipment may sometimes be conducted after carrying out the sampling test following the final test.